The present invention relates generally to digital-to-analog conversion of electrical signals, and more particularly to a high-precision, low-current current-steering digital-to-analog converter.
A digital-to-analog converter (DAC) converts a digital input signal represented by a number of bits N to a substantially equivalent analog output signal. The analog output signal is typically a voltage or current signal.
A typical DAC for converting the digital input signal into an analog current output signal is a current-steering DAC. In one type of current-steering DAC, a reference voltage is converted into binary-weighted currents. For example, in one such current-steering DAC, switches couple each input of parallel coupled binary weighted resistors to either a reference voltage or ground depending on whether the digital input signal bit is a logic 1 level or a logic 0 level. The outputs of each of the binary weighted resistors are coupled to an output current node.
Another example of a current-steering DAC employs an R-2R ladder coupled to a reference voltage. Switches are coupled in parallel to outputs of the R-2R resistor ladder. The switches are controlled by digital input signal bits to couple the current from the outputs of the R-2R resistor ladder to ground when the digital input signal bit is at a logic 0 level or to a current output node when the digital input signal bit is at a logic 1 level.
The present invention provides a digital-to-analog converter (DAC) and a method for converting a digital input signal having N bits to a substantially equivalent analog current output signal. The DAC of the invention utilizes bit segmentation and shared reference current(s) to allow high precision, high linearity, and a high input signal bit count resulting from the ability to ensure CMOS FET saturation even in the submicron and deep submicron process technologies.
In accordance with the invention, the N-bit binary digital input signal is segmented into at least a first group of i bits and a second group of j bits. The DAC of the invention includes a first current-steering digital-to-analog converter configured to receive the first group of i bits and a first reference current that produces a first digital-to-analog converter output current representation based on the value of the first group of i digital bits. The DAC also includes at least a second current-steering digital-to-analog converter configured to receive the second group of j bits of the N-bit binary digital input signal and the first reference current. The second current-steering digital-to-analog converter produces a second digital-to-analog converter output current representative of a value of the second group of j bits. The second digital-to-analog converter output current is scaled down by an order of magnitude substantially equal to 2j by a current scaling circuit. The DAC includes a summing circuit which sums at least the first digital-to-analog converter output current and the scaled down version of the second digital-to-analog converter output current to produce an analog current signal representative of the value of the N-bit binary input signal.
In a preferred embodiment, the DAC includes a binary-to-thermometer encoder dedicated to each segmented group i, j of digital input signal bits. A first binary-to-thermometer encoder converts the first group of i bits to a thermometer code represented by 2i thermometer code bits, and a second binary-to-thermometer encoder converts the second group of j bits to a thermometer code represented by 2j thermometer code bits. Additional binary-to-thermometer encoders may be used if the digital input signal of N bits is further segmented into additional segmented groups of bits kx.
The DAC also includes a group of identical current source arrays dedicated to each segmented group i, j of digital input signal bits. More particularly, the DAC includes at least a first array of 2i identical current sources each of which is selectable by a respective one of the 2i thermometer code bits to contribute an identical current referenced by a first reference current to an output line. The sum of the identical currents contributed by the first array of 2i identical current sources is therefore summed on the output line. The DAC further includes at least a second array of 2j identical current sources each of which is selectable by a respective one of the 2j thermometer code bits to contribute an identical current referenced by a first reference current to an intermediate output line. The sum of the identical currents contributed by the second array of 2j identical current sources is therefore summed on the intermediate output line.
The DAC also includes a current dividing circuit which divides the total current present on the intermediate output line by 2j. The divided current is added to the current on the output line. Accordingly, an analog current signal representation of the digital input signal is produced on the output line of the DAC.
In a preferred embodiment, a 16-bit DAC is implemented with a 4-6-6 bit grouping, with the 4 highest significant bits encoded to generate a 24-bit thermometer code, the next 6 highest significant bits encoded to generate a 26-bit thermometer code, and the lowest 6 significant bits encoded to generate a 26-bit thermometer code. In this embodiment, the high thermometer code bits are fed to a high current source array comprising 24 current sources. Each current source is selectable by a different one of the 24 bits of the high thermometer code. When a high thermometer code bit is asserted, its respective current source generates a current substantially equal to a high reference current.
The mid thermometer code bits are fed to a mid current source array comprising 26 current sources. Each current source in the mid current source array is selectable by a different one of the 26 bits of the mid thermometer code. When a mid thermometer code bit is asserted, its respective current source generates a current substantially equal to a mid reference current.
The low thermometer code bits are fed to a low current source array comprising 26 current sources. Each current source in the low current source array is selectable by a different one of the 26 bits of the low thermometer code. When a low thermometer code bit is asserted, its respective current source generates a current substantially equal to the mid reference current. The total current contributed by each of the low current sources is summed on an intermediate output line, which is fed to a divider circuit that divides the summed outputs from the current sources in the low current source array by 26 to scale down the current.
The total current contributed by each of the selected high current sources, each of the selected mid current sources, and the current output by the current divider is summed to produce an analog current signal representation of a given 16-bit digital input signal.
The segmentation and sharing of a mid-level reference current with the lowest-level segmented DAC allows the current-steering DAC of the invention to handle subthreshold current LSB""s in a submicron process while maintaining very good linearity. In particular, this entails the sharing of references (Low, Mid) so the current mirror arrays are xe2x80x9cidenticalxe2x80x9d and the divide-by-64 current circuit that generates the lowest 6 bits of the 16-bit DAC.